1. Field of the Invention
The present invention relates to a package and a method of making the same, and more particularly to a three-dimensional package and a method of making the same.
2. Description of the Related Art
Referring to FIG. 1, it shows a schematic view of a three-dimensional package before reflow disclosed in U.S. Pat. No. 4,499,655. The three-dimensional package 1 comprises a first unit 10 and a second unit 20. The first unit 10 comprises a first semiconductor body 11, at least one first hole 12, a first conductive layer 13 and a first solder 14. The first semiconductor body 11 has a first surface 111 and a second surface 112. The first surface 111 has at least one first pad (not shown) and a first protection layer 113 exposing the first pad. The first hole 12 penetrates the first semiconductor body 11. The first conductive layer 13 is disposed on the side wall of the first hole 12 and covers the first pad and the first protection layer 113. The first solder 14 is disposed in the first hole 12 and is electrically connected to the first pad via the first conductive layer 13. The upper end of the first solder 14 extends to above the first surface 111 of the first semiconductor body 11, and the lower end of the first solder 14 extends to below the second surface 112 of the first semiconductor body 11.
The second unit 20 is stacked on the first unit 10. The second unit 20 comprises a second semiconductor body 21, at least one second hole 22, a second conductive layer 23 and a second solder 24. The second semiconductor body 21 has a first surface 211 and a second surface 212. The first surface 211 has at least one second pad (not shown) and a second protection layer 213 exposing the second pad. The second hole 22 penetrates the second semiconductor body 21. The second conductive layer 23 is disposed on the side wall of the second hole 22 and covers the second pad and the second protection layer 213. The second solder 24 is disposed in the second hole 22 and is electrically connected to the second pad via the second conductive layer 23. The upper end of the second solder 24 extends to above the first surface 211 of the second semiconductor body 21, and the lower end of the second solder 24 extends to below the second surface 212 of the second semiconductor body 21. The lower end of the second solder 24 is aligned with and contacts the upper end of the first solder 14. After performing a reflow process, the first unit 10 and the second unit 20 are joined to form a three-dimensional package 1, as shown in FIG. 2.
In the three-dimensional package 1, the first solder 14 and the second solder 24 are formed by disposing the first semiconductor body 11 and the second semiconductor body 21 above a solder bath, and the solder enter the first hole 12 and the second hole 22 according to the capillary phenomenon so as to form the first solder 14 and the second solder 24.
The disadvantages of the three-dimensional package 1 are described as follows. As the first solder 14 and the second solder 24 are formed according to the capillary phenomenon, the upper and the lower ends of the foregoing solders are in a hemispherical shape (FIG. 1). As such, when the first unit 10 and the second unit 20 are aligned and joined, alignment becomes more difficult and the joining between the first unit 10 and the second unit 20 after reflow is not stable. Moreover, after the joining of the first unit 10 and the second unit 20, the overall height cannot be effectively reduced due to the excess hemispherical solders.
Therefore, it is necessary to provide a three-dimensional package and a method of making the same to solve the above problems.